The disclosures herein relate generally to integrated circuits, and more particularly to a CMOS based thermopile with reduced electrical resistance.
Thermoelectric devices, which are fabricated as parts of integrated circuits in which the thermoelectric elements are formed of silicon, tend to have poor performance due to higher electrical resistance through the thermoelectric elements and the substrate regions between adjacent thermoelectric elements than desired. Integrating low electrical resistance thermoelectric elements and connecting substrate regions into an integrated circuit containing complementary metal oxide semiconductor (CMOS) transistors has been problematic.